? semiconductor components industries, llc, 2006 november, 2006 ? rev. 8 1 publication order number: mc10h640/d mc10h640, mc100h640 68030/040 pecl to ttl clock driver description the mc10h/100h640 generates the necessary clocks for the 68030, 68040 and similar microprocessors. it is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part ? to ? part skew, within ? part skew and also duty cycle skew. the user has a choice of using either ttl or pecl (ecl referenced to +5.0 v) for the input clock. ttl clocks are typically used in present mpu systems. however, as clock speeds increase to 50 mhz and beyond, the inherent superiority of ecl (particularly differential ecl) as a means of clock signal distribution becomes increasingly evident. the h640 also uses differential pecl internally to achieve its superior skew characteristic. the h640 includes divide ? by ? two and divide ? by ? four stages, both to achieve the necessary duty cycle skew and to generate mpu clocks as required. a typical 50 mhz processor application would use an input clock running at 100 mhz, thus obtaining output clocks at 50 mhz and 25 mhz (see logic diagram). features ? generates clocks for 68030/040 ? meets 030/040 skew requirements ? ttl or pecl input clock ? extra ttl and pecl power/ground pins ? asynchronous reset ? single +5.0 v supply ? pb ? free packages are available* function reset (r): low on reset forces all q outputs low and all q outputs high. power ? up: the device is designed to have the pos edges of the 2 and 4 outputs synchronized at power up. select (sel): low selects the ecl input source (de/de ). high selects the ttl input source (dt). the h640 also contains circuitry to force a stable state of the ecl input differential pair, should both sides be left open. in this case, the de side of the input is pulled low, and de goes high. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram* xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package plcc ? 28 fn suffix case 776 mcxxxh640g awlyyww 1 http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions sect ion on page 7 of this data sheet. ordering information
mc10h640, mc100h640 http://onsemi.com 2 1 vt vt q1 gt gt q0 vt gt gt q4 q5 vt sel 56 7891011 25 24 23 22 21 20 19 q1 figure 1. pinout: plcc ? 28 (top view) v bb de de ve r ge dt q0 vt vt q3 gt gt q2 4 3 2 28 27 26 18 17 16 15 14 13 12 figure 2. logic diagram ttl outputs ttl/ecl clock inputs ttl control inputs v bb de dt sel r de mux 2 4 q0 q1 q2 q3 q0 q1 q4 q5 table 1. pin description pin function gt vt ve ge de, de v bb dt qn, qn sel r ttl ground (0 v) ttl v cc (+5.0 v) ecl v cc (+5.0 v) ecl ground (0 v) ecl signal input (positive ecl) v bb reference output ttl signal input signal outputs (ttl) input select (ttl) reset (ttl) table 2. dc characteristics (v t = v e = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c min max min max min max unit i ee power supply current ecl ve pin 57 57 57 ma i cch ttl total all vt pins 30 30 30 ma i ccl 30 30 30 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
mc10h640, mc100h640 http://onsemi.com 3 table 3. 10h pecl dc characteristics (v t = v e = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min max min max i inh i inl input high current input low current 0.5 255 0.5 175 0.5 175 a v ih 1 v il 1 input high voltage input low voltage v e = 5.0 v 3.83 3.05 4.16 3.52 3.87 3.05 4.19 3.52 3.94 3.05 4.28 3.555 v v bb 1 output reference voltage 3.62 3.73 3.65 3.75 3.69 3.81 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. pecl levels are referenced to v cc and will vary 1:1 with the power supply. the values shown are for v cc = 5.0v. table 4. 100h pecl dc characteristics (v t = v e = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min max min max i inh i inl input high current input low current 0.5 255 0.5 175 0.5 175 a v ih 2 v il 2 input high voltage input low voltage v e = 5.0 v 3.835 3.19 4.12 3.525 3.835 3.19 4.12 3.525 3.835 3.19 4.12 3.525 v v bb 2 output reference voltage 3.62 3.74 3.62 3.74 3.62 3.74 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. pecl levels are referenced to v cc and will vary 1:1 with the power supply. the values shown are for v cc = 5.0v. table 5. ttl dc characteristics (v t = v e = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min max min max v ih v il input high voltage input low voltage 2.0 0.8 2.0 0.8 2.0 0.8 v i ih input high current v in = 2.7 v v in = 7.0 v 20 100 20 100 20 100 a i il input low current v in = 0.5 v ? 0.6 ? 0.6 ? 0.6 ma v oh output high voltage i oh = ? 3.0 ma i oh = ? 15 ma 2.5 2.0 2.5 2.0 2.5 2.0 v v ol output low voltage i ol = 24 ma 0.5 0.5 0.5 v v ik input clamp voltage i in = ? 18 ma ? 1.2 ? 1.2 ? 1.2 v i os output short circuit current v out = 0 v ? 100 ? 225 ? 100 ? 225 ? 100 ? 225 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
mc10h640, mc100h640 http://onsemi.com 4 table 6. ac characteristics (v t = v e = 5.0 v 5%) symbol characteristic condition 0 c 25 c 85 c unit min max min max min max t plh propagation delay ecl d to output q0 ? q3 cl = 25 pf 4.0 6.0 4.0 6.0 4.2 6.2 ns t plh propagation delay ttl d to output cl = 25 pf 4.0 6.0 4.0 6.0 4.3 6.3 ns tskwd* within ? device skew cl = 25 pf 0.5 0.5 0.5 ns t plh propagation delay ecl d to output q0 , q1 cl = 25 pf 4.0 6.0 4.0 6.0 4.2 6.2 ns t plh propagation delay ttl d to output cl = 25 pf 4.0 6.0 4.0 6.0 4.3 6.3 ns t plh propagation delay ecl d to output q4, q5 cl = 25 pf 4.0 6.0 4.0 6.0 4.2 6.2 ns t plh propagation delay ttl d to output cl = 25 pf 4.0 6.0 4.0 6.0 4.3 6.3 ns t pd propagation delay r to output all outputs cl = 25 pf 4.3 6.3 4.3 6.3 5.0 7.0 ns t r t f output rise/fall time 0.8 v to 2.0 v all outputs cl = 25 pf 2.5 2.5 2.5 2.5 2.5 2.5 ns f max maximum input frequency cl = 25 pf 135 135 135 mhz t pw minimum pulse width 1.50 1.50 1.50 ns t rr reset recovery time 1.25 1.25 1.25 ns note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. within ? device skew defined as identical transitions on similar paths through a device. table 7. v cc and c l ranges to meet duty cycle requirements (0 c t a 85 c output duty cycle measured relative to 1.5 v) symbol characteristic condition min nom max unit range of v cc and cl to meet mini- mum pulse width (high or low) = 11.5 ns at f out 40 mhz v cc cl q0 ? q3 q0 ? q1 4.75 10 5.0 5.25 50 v pf range of v cc and cl to meet mini- mum pulse width (high or low) = 9.5 ns at 40 < f out 50 mhz v cc cl q0 ? q3 4.875 15 5.0 5.125 27 v pf
mc10h640, mc100h640 http://onsemi.com 5 10 11 9 0 25507585 5.25 v cc 5 v cc 4.75 v cc pw (ns) figure 3. positive pulse width at 25 c ambient and 50 mhz out load (pf) 10 11 9 0 25507585 figure 4. negative pulse width at 25 c ambient and 50 mhz out load (pf) negative pulse width (ns) 4.75 v cc 5 v cc 5.25 v cc 10 11 9 0 25507585 load (pf) figure 5. positive pulse width at 25 c ambient at 50 mhz out positive pulse width (ns) 5.125 v cc 5 v cc 4.875 v cc 10 11 9 0 25507585 negative pulse width (ns) load (pf) figure 6. negative pulse width at 25 c ambient at 50 mhz out 4.875 v cc 5 v cc 5.125 v cc 10 11 9 0 25 50 75 85 50 pf 25 pf 10 pf figure 7. temperature versus positive pulse width for 100h640 at 50 mhz and v cc = +5.0 v temperature ( c) positive pulse width (ns) 10 11 9 0 25 50 75 85 10 pf 25 pf figure 8. temperature versus negative pulse width for mc100h640 @ 50 mhz and v cc = +5.0 v temperature ( c) negative pulse width (ns) 10/100h640 duty cycle control to maintain a duty cycle of 5% at 50mhz, limit the load capacitance and/or power supply variation as shown in figures 3 and 4. for a 2.5% duty cycle limit, see figures 5 and 6. figures 7 and 8 show duty cycle variation with temperature. figure 9 shows typical tpd versus load. figure 10 shows reset recovery time. figure 11 shows output states after power up. best duty cycle control is obtained with a single p load and minimum line length.
mc10h640, mc100h640 http://onsemi.com 6 5.8 6.2 5.4 0 25 50 75 85 figure 9. t pd versus load typical at t a = 25 c t pd c load (pf) 4.75 v 5 v 5.25 v figure 10. mc10h/100h640 clock phase and reset recovery time after reset pulse dt reset, r q0, q1, q2, q3 q0 , q1 q4, q5 r trec r tpw figure 11. output timing diagram after power up outputs q 4 & q 5 will sync with positive edges of d in & q 0 q 3 & negative edges of q 0 & q 1 d in q 0 q 3 q 1 q 2 q 4 & q 5 5.2 5.6 6.0 (ns)
mc10h640, mc100h640 http://onsemi.com 7 ordering information device package shipping ? mc10h640fn plcc ? 28 37 units / rail mc10h640fng plcc ? 28 (pb ? free) 37 units / rail mc10h640fnr2 plcc ? 28 500 / tape & reel mc10h640fnr2g plcc ? 28 (pb ? free) 500 / tape & reel mc100h640fn plcc ? 28 37 units / rail mc100h640fng plcc ? 28 (pb ? free) 37 units / rail MC100H640FNR2 plcc ? 28 500 / tape & reel MC100H640FNR2g plcc ? 28 (pb ? free) 500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc10h640, mc100h640 http://onsemi.com 8 package dimensions plcc ? 28 fn suffix plastic plcc package case 776 ? 02 issue e ? n ? ? m ? ? l ? v w d d y brk 28 1 view s s l?m s 0.010 (0.250) n s t s l?m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l?m m 0.007 (0.180) n s t ? t ? b s l?m s 0.010 (0.250) n s t s l?m m 0.007 (0.180) n s t u s l?m m 0.007 (0.180) n s t z g1 x view d ? d s l?m m 0.007 (0.180) n s t k1 view s h k f s l?m m 0.007 (0.180) n s t notes: 1. datums ?l?, ?m?, and ?n? determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?t?, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 ??? 0.51 ??? k 0.025 ??? 0.64 ??? r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y ??? 0.020 ??? 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 ??? 1.02 ???
mc10h640, mc100h640 http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc10h640/d eclinps is a trademark of semiconductor components industries, llc (scillc). mecl 10h is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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